1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a non-volatile ferroelectric memory.
2. Background of the Related Art
The ferroelectric memory, i.e., an FRAM (Ferroelectric Random Access Memory), having in general a data processing speed similar to a DRAM (Dynamic Random Access Memory) used widely as a semiconductor memory and being capable of conserving data even if the power is turned off, is paid attention as a next generation memory. The FRAM, a memory having a structure similar to the DRAM, is provided with a capacitor of a ferroelectric material for utilizing a high residual polarization of the ferroelectric material. The residual polarization permits the conservation of a data even after removal of an electric field.
FIG. 1 illustrates a characteristic curve of a hysteresis loop of a general ferroelectric material.
Referring to FIG. 1, it can be known that a polarization induced by an electric field is, not erased, but, certain amount (`d` and `a` states) of which is remained, even if the electric field is removed owing to existence of the residual polarization (or spontaneous polarization). The `d` and `a` states are corresponded to `1` and `0` respectively in application to memories.
A related art non-volatile ferroelectric memory will be explained with reference to the attached drawings. FIG. 2 illustrates a system of unit cell of the related art non-volatile ferroelectric memory.
Referring to FIG. 2, the system of unit cell of the related art non-volatile ferroelectric memory is provided with a bitline B/L formed in one direction, a wordline W/L formed in perpendicular to the bitline, a plateline P/L formed spaced from the wordline in a direction identical to the wordline, a transistor T1 having a gate connected to the wordline and a source connected to the bitline, and a ferroelectric capacitor FC1 having a first terminal connected to a drain of the transistor T1 and a second terminal connected to the plateline P/L.
A circuit for driving the related art ferroelectric memory will be explained. FIGS. 3A and 3B illustrate a circuit for driving the related art ferroelectric memory.
The circuit for driving the related art ferroelectric memory of an 1T/1C structure is provided with a reference voltage generator 1 for generating a reference voltage, a reference voltage stabilizer 2 having a plurality of transistors Q1.about.Q4 and a capacitor C1 for stabilizing reference voltages on adjacent two bitlines, a first reference voltage storage 3 having a plurality of transistors Q6-Q7, and capacitors C2-C3 for respectively storing logical values of "1" and "0" on adjacent bitlines, a first equalizer 4 having a transistor Q5 for equalizing adjacent two bitlines, a first main cell array 5 connected to wordlines and platelines different from each other for storing data, a first sense amplifier 6 having a plurality of transistors Q10.about.Q15, a P-sense amplifier PSA for sensing data in cells selected by the wordline among the plurality of cells in the first main cell array 5, a second main cell array 7 connected to wordlines and platelines different from one another for storage of data, a second reference voltage storage 8 having a plurality of transistors Q28.about.Q29 and capacitors C9.about.C10 for storing reference voltages with logical values of "1" and "0" on adjacent bitlines, and a second sense amplifier 9 having a plurality of transistors Q16.about.Q25, N-sense amplifier NSA for sensing and forwarding a data in the second main array 7.
The data input/output operation of the related art ferroelectric memory will be explained. FIG. 4 illustrates a timing diagram of a write mode operation of the related art ferroelectric memory, and FIG. 5 illustrates a timing diagram of a read mode operation of the related art ferroelectric memory.
In writing, when an external chip enable signal CSB pad is enabled from `high` to `low` and a write enable signal WEBpad is applied from `high` to `low` on the same time, a write mode is started. When address decoding is started in the write mode, a pulse applied to a relevant wordline is transited from `low` to `high` to select a cell. Thus, in an interval the wordline is held `high`, a relevant plateline is applied of a `high` signal for one interval and a `low` signal for the other interval in succession. And, in order to write a logical value `1` or `0` on the selected cell, a `high` or `low` signal synchronized to the write enable signal WEBpad is applied to a relevant bitline. That is, if a `high` signal is applied to the bitline and a signal applied to the plateline is `low` in an interval in which a signal applied to the wordline is `high`, a logical value `1` is written on the ferroelectric capacitor. And, if a `low` signal is applied to the bitline and a signal applied to the plateline is `high`, a logical value `0` is written on the ferroelectric capacitor.
The operation for reading the data stored in the cell by the aforementioned write mode operation will be explained.
If the chip enable signal CSBpad is enabled from `high` to `low` externally, all bitlines are equalized to a `low` voltage before a relevant wordline is selected. That is, referring to FIGS. 3A and 3B, if a `high` signal is applied to the equalizer 4 and a `high` signal is applied to the transistors Q18 and Q19, as the bitlines are grounded through the transistor Q19, the bitlines are equalized to a low voltage Vss. And, the transistors Q5, Q18, and Q19 are turned off, to disable the bitlines, an address is decoded, and the decoded address causes a `low` signal on a relevant wordline to transit to a `high` signal, to select a relevant cell. A `high` signal is applied to the plateline of the selected cell, to break a data corresponding to a logical value `1` stored in the ferroelectric memory. If a logical value `0` is in storage in the ferroelectric memory, a data corresponding to the logical value `0` is not broken. The data not broken and the data broken provide values different from each other according to the aforementioned hysteresis loop, so that the sense amplifier senses a logical value `1` or `0`. The case of the data broken is a case when the value is changed from `d` to `f` in the hysteresis loop of FIG. 1, and the case of the data not broken is a case when the value is changed from `a` to `f` in the hysteresis loop of FIG. 1. Therefore, if the sense amplifier is enabled after a certain time period is passed, in the case of the data broken, a logical value `1` is provided as amplified, and in the case of the data not broken, a logical value `0` is provided. After the sense amplifier provides data thus, in order to restore an original data, the plateline is disabled from `high` to `low` in a state a `high` signal is applied to a relevant wordline. In the related art ferroelectric memory of an 1T/1C structure, data input/output operations of the reference cell require much more operation than the operations of the main cell.
The aforementioned related art ferroelectric memory has the following problem.
The use of one reference cell in reading main cells of a number a few hundred times. greater than the reference cell under a state a ferroelectric characteristic is not assured adequately, that requires the reference cell much more operation than the main cells, causes a rapid degradation of the reference cell, resulting in a voltage instability, device operation characteristics deterioration, and short lifetime.